We need to make it easier to design custom accelerators, especially for reconfigurable hardware (i.e., FPGAs). The current mainstream options are hardware description languages (HDLs), which are low-level languages that make it feel like you’re wiring up a circuit by hand, and high-level synthesis (HLS) tools, which compile legacy software languages like C or C++ to an HDL.
The thesis of this talk is that better alternatives are possible. Perhaps unsurprisingly, we find that the semantic chasm between C++ and hardware circuits comes with myriad correctness and performance pitfalls. We advocate instead for more research on accelerator design languages: programming models that maintain computational semantics while not attempting to shield developers from thinking about hardware. Our lab is working on a programming language, Dahlia, that uses a type system to restrict HLS programs to a subset with predictable semantics and performance. Based on Dahlia, we are designing a compiler infrastructure to support the construction of new accelerator design languages.